1. Field of the Invention
The present invention refers to an integrated circuit chip having a number of pads to connect an integrated circuit. The present invention further refers to an integrated device including a packaged integrated circuit chip and interconnection means.
2. Description of the Related Art
The electrical performance of integrated devices increasingly develops into a limiting factor in high-speed memory packages, e.g. for graphics applications. Proper signal routing, particularly in a package, becomes more and more important for the signal quality. The signal routing comprises the signal trace and the corresponding return path through power and ground planes/traces. One of the main issues is the noise generated by the non-ideal power supply system. To reduce the noise, the inductance of the loop power supply/ground-signal-trace has to be minimized and the required line characteristic impedance has to be maintained constantly along the whole signal path.
Although the loop inductance can be minimized and the required impedance of the package can be achieved by means of routing measures, the bonding wires within the package seem to limit the high frequency package performance. The reason is that there is an additionally remaining inductance for the signal and power lines.
Dual slot FBGA packages reduce the length of bonding wires for power supply planes, but with today's pad arrangement on the chip the inductance of the signal bond wires and the signal-to-power coupling within the bond wire region cannot be affected significantly. Moreover, the distance between the signal and the supply bond wires is limited by the pad pitch and cannot be reduced by shrinking the feature sizes due to restrictions of the bonding equipment.
For example, on a FBGA substrate the signal-to-power/ground loop inductance can be minimized by reducing the total length of the signal/power supply line as much as possible by routing the signal bond wires as close as possible to the corresponding power/ground supply lines and maintaining the trace widths/spacings all along the path constant to achieve a constant line impedance. In the area of the bond channel through which the bond wires are led, a constant impedance cannot be achieved as the bond wires have a predominantly inductive behaviour and the spacings between the signal and power/ground supply bond wires are defined by the chip pad arrangement. Consequently, the result is an impedance discontinuity of bond wires which can only be minimized by shortening the bond wires wherever possible.
One approach used where the overall loop inductance in a high frequency application becomes critical due to the bond wire inductance, is a flip-chip design. However, this approach leads to increased packaging costs.